Electronics and Communication Engineering – Embedded System and VLSI Design
Introduction to course
Welcome to our M.Tech. Program in Electronics and Communication Engineering – Embedded System and VLSI Design, where we delve into the heart of cutting-edge technology. This program is tailored for aspiring engineers passionate about designing and developing innovative electronic systems at both the hardware and software levels. Through a comprehensive curriculum, hands-on projects, and industry collaborations, students explore advanced topics such as embedded systems, Very Large Scale Integration (VLSI) design, and system-on-chip (SoC) architecture.
Mission
We aim to provide a stimulating learning environment that encourages innovation, critical thinking, and collaboration. Our mission is to empower students to excel in the design and implementation of cutting-edge electronic devices and systems. Through a combination of theoretical knowledge and practical experience, we prepare our graduates to become leaders and innovators in the field of electronics and communication engineering, driving technological advancements and contributing to the betterment of society.
Vision
We envision a future where our graduates are esteemed for their expertise, creativity, and leadership in designing innovative electronic systems. Through cutting-edge research, industry partnerships, and interdisciplinary collaborations, we aspire to shape the future of electronics and communication technology. Our aim is to inspire the next generation of engineers to push the boundaries of embedded systems and VLSI design, driving advancements and creating solutions that address the challenges of the digital age.
Course objective
- Gain a thorough understanding of embedded systems architecture, design principles, and programming techniques.
- Develop proficiency in designing and implementing intricate digital systems using advanced Very Large Scale Integration (VLSI) design methodologies.
- Explore cutting-edge concepts like system-on-chip (SoC) architecture, hardware/software co-design, and real-time operating systems.
- Enhance problem-solving abilities through practical projects, laboratory experiments, and case studies focused on embedded system and VLSI design.
- Prepare for diverse career opportunities in the semiconductor industry, embedded systems sector, research organizations, and academia, supported by comprehensive academic training and hands-on experience.
Course outcome
- Mastery in designing and implementing embedded systems using advanced architectures and programming techniques.
- Proficiency in developing complex digital systems through VLSI design methodologies, including RTL design and synthesis.
- Understanding of SoC architectures and the integration of hardware and software components.
- Application of real-time operating systems and hardware/software co-design techniques to optimize embedded system performance.
- Effective communication of technical concepts and findings, alongside collaboration skills demonstrated in team-based projects.
Admission procedure
Check Eligibility (Physics + Maths + Chemistry / Computer)
|
Board |
Category |
Theory Marks |
Theory + Practical Marks |
|---|---|---|---|
|
GSEB |
Open |
135 / 300 |
180 / 400 |
|
GSEB |
Reserve |
120 / 300 |
180 / 400 |
|
Other Boards |
Open |
108 / 240 |
135 / 300 |
|
Other Boards |
Reserve |
96 / 240 |
120 / 300 |
Required Documents
- SSC
- HSC
- GUJCET mark-sheet
- Leaving certificate (applicable for all)
- Income certificate
- Caste certificate, NCL (if applicable)
Curriculum
- Duration: 4 years
- Fees: Rs. 70,000
- Intake: 60
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| GTU Code | Subject | Theory(Hrs) | Tutorial(Hrs) | Practical(Hrs) | Credits |
|---|---|---|---|---|---|
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
| 3110000 | Lorem Ipsum | 0 | 0 | 0 | 0 |
Faculty
Labs and facilities
Photo gallery
